1. Field of the Invention
The present invention relates to the structure of and a method of fabricating deep trench dynamic random access memory (DRAM) using silicon on insulator (SOI) substrate and shallow trench isolation (STI) technologies. The deep trench DRAM of the present invention enables a greater density of devices on a DRAM memory chip. The present invention also simplifies the process for making deep trench DRAM by reducing the number of steps in the fabrication process over the prior art. Furthermore, the present invention has minimized electrical interaction, such as latchup, between devices of the DRAM.
2. Description of the Prior Art
Silicon on insulator (SOI) substrates are well known in the field of semiconductor fabrication for providing several advantages over standard silicon substrates. Building transistor devices on SOI substrates provides a lower substrate capacitance, reduces susceptibility to radiation damage, and also permits the use of a lower voltage for device operation. Several previous inventions exist which employ SOI substrates in combination with deep trench capacitors in various configurations.
Kleinhenz (U.S. Pat. No. 5,770,484) describes a trench capacitor and an SOI substrate. The deep trench capacitor is formed by a two-part etching process. A first trench is formed through a buried insulator layer, and a diffusion barrier collar is then formed on the sidewall of the first trench. Next, a second trench below the first trench is formed without any barriers on the sidewall, and the deep trench is filled with a doped poly-Si plug. A buried strap, comprising poly-Si, is deposited above the plug and makes contact with the SOI substrate containing the devices. Yoon (U.S. Pat. No. 4,999,312) describes a process for forming a trench capacitor similar to the Kleinhenz method, but Yoon""s device is built on a silicon substrate. Watanabe (U.S. Pat. No. 5,309,008) discloses a top trench with a slightly larger diameter than a bottom trench formed beneath the top trench. The sidewall of the top trench is lined with an insulating diffusion barrier, and the sidewall of the bottom trench is diffused with dopants and serves as a capacitor electrode. Hsu et al. (U.S. Pat. No. 5,384,277) is directed to a method of forming a MOS DRAM simplified by combining the process for making a capacitor-drain strap with the process for forming a source/drain contact. Rajeevakumar (U.S. Pat. No. 5,406,515) describes low leakage trenches for DRAM comprising the formation of a diffusion ring in the upper part of the trench wall in the n-well region for reducing storage charge leakage. CMOS devices are built in an n-well formed in a p-epi layer over a p+substrate. Bronner et al. (U.S. Pat. No. 5,508,219) describes DRAM employing SOI with a trench capacitor. A strap poly-Si layer within the trench is used to form the connection between the poly-Si trench capacitor electrode and the side of the device layer, or drain region, of the SOI. Hayashi (U.S. Pat. No. 4,820,652) teaches an integrated process that fabricates a trench capacitor and an SOI wafer by epitaxial overgrowth. The inner electrode is connected to the transistor using a strap, and the trench is purposely offset with respect to the opening in the buried oxide allowing the trench capacitor plate sidewall to connect to the epitaxial layer.
These conventional processes to produce deep trench DRAM, however, suffer certain deficiencies. In the conventional processes the deep trenches are formed by etching through the SOI device layer and into the silicon substrate. Because no portion of the device layer remains above the trench, a field effect transistor (FET) comprising a source, drain and channel region in the device layer cannot reside above the trench. As a result, the connection between the trench capacitor electrode, formed within the trench, and the subsequently formed FET devices must be made through a sideways strap connection. More importantly, though, the inability to place devices above the trench leads to an inefficient use of space on the DRAM chip. Because the devices in the conventional processes must reside next to the trenches rather than above the trenches, the space above the trenches is often wasted. Additionally, in traditional devices, the buried strap connection becomes problematic when the dimensions of the chip are reduced; these problems include leakage currents and high resistance. Further evolution in the memory technology depends, not only on reduction in design feature size, but also on efficient use of the space available on the memory chip and on new methods for establishing connections between the capacitor and the active area.
Therefore, there is still a need for an improved process for forming a deep trench DRAM using an SOI substrate that reduces the number of steps required to produce a DRAM, improves the connection between the capacitor and the active area, and makes more efficient use of the space available on the DRAM.
Accordingly, the present invention is directed to a method of forming a semiconductor device and to a semiconductor device that substantially obviate one or more of the problems due to the limitations and disadvantages of the prior art. To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention can comprise a method of forming a semiconductor device including (1) forming a masking layer on a silicon substrate and patterning an opening for etching a deep trench, (2) forming the deep trench for a DRAM capacitor by anisotropic etching, thereby forming the first electrode of the capacitor, (4) forming a node dielectric layer on the trench sidewall, (5) filling the trench with poly-Si to serve as the second electrode of the trench capacitor, (6) using wet etching and chemical mechanical polishing (CMP) to provide a flat surface above the trench, (7) forming an insulator layer, (8) opening the insulator layer to enable connection to the second electrode of the trench capacitor, (9) using SOI technology to form an active area of Si, and (10) using a shallow trench isolation (STI) technique for isolating the active area.
A semiconductor device formed by the method of the present invention has several advantages. By forming the deep trench capacitor prior to deposition of the SOI substrate, a connection between the active layer, or device layer, of the SOI substrate and the second electrode can be made directly above the deep trench capacitor. This arrangement enables fabrication of devices in the area above the deep trench capacitor to produce DRAM exhibiting efficient use of available chip space. The DRAM produced by the method of the present invention can have a higher density of devices on the surface of the chip than the DRAM of the prior art. It also provides an improved connection between the active area and the capacitor of the DRAM, and remedies the buried strap connection problems of the prior art.
Additional advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the invention and together with the description, serve to explain the principles of the invention.